BK

👋 Hi there, I'm

Bharadhwaj K

I build |

Research Intern at CHIPS, PES University. Building at the intersection of Hardware & Software — from RISC-V processors to scalable web applications.

0+ Projects
0+ Years Exp
0+ Technologies
Developer
engineer.py
class Engineer:
    def __init__(self):
        self.name = "Bharadhwaj"
        self.role = "ECE + Software"
        self.hardware = [
            "RISC-V",
            "RTL"
        ]
        self.software = [
            "Full-Stack",
            "AI/ML"
        ]
Scroll Down

02. About Me

I'm an Electronics and Communication Engineering student at PES University with strong foundations in both computer architecture and software engineering.

Currently researching RISC-V performance optimization at CHIPS Lab, while also building full-stack applications and AI/ML pipelines. I bridge the gap between hardware and software.

Whether it's writing RTL for processors or deploying microservices, I enjoy solving complex problems across the entire computing stack.

Education

B.Tech in ECE

PES University • 2022-2026 CGPA: 7.29/10

Location

Bangalore, India

Open to opportunities
Coding Setup

03. Experience

Research Intern @ CHIPS, PES University

May 2025 — Present

  • Conducting research on performance analysis and optimization techniques for RISC-V systems
  • Developing cycle-accurate profiling tools using Python and C++ for processor performance analysis
  • Building automation scripts for data collection, preprocessing, and analysis pipelines
  • Integrating profiler with InCore's Azurite core for testing and validation
RISC-V Python C++ Verilator Linux

Teaching Assistant @ PES University

Aug 2024 — Jan 2025

  • Technical TA for 5-day workshop on Standard Cell Design using SCL PDK 180nm (NXP Semiconductors)
  • Guided 60+ participants through complete backend flow including custom layout and characterization
  • Conducted workshops on RTL-to-GDS flow and digital design concepts
  • Mentored students on technical projects and helped debug complex issues
VLSI Digital Design Cadence RTL

04. Featured Projects

Book Recommendations
Featured Project

Book Recommendations Microservices

Microservices architecture for book recommendations with user authentication, recommendation engine, and real-time notifications.

Python FastAPI Docker Redis PostgreSQL
RISC-V Profiler
Research Project • IEEE HiPC 2025

PARISCV: RISC-V Performance Profiler

Profiling application for RISC-V instruction analysis. Poster presented at IEEE HiPC 2025, Hyderabad.

Python C++ RISC-V Spike
Admissions CRM
Full-Stack Application

Admissions CRM System

Complete CRM solution for managing student admissions with lead tracking, analytics dashboard, and automated workflows.

Next.js TypeScript Supabase Tailwind
Trading Bot
FinTech

Binance Futures Trading Bot

Algorithmic trading bot for Binance Futures with order management, real-time monitoring, and comprehensive logging system.

Python AsyncIO REST APIs WebSocket
Web Development
Web Development

PES-IEEE Conference Site

Full-stack conference website handling 500+ attendees with dynamic navigation, server-side rendering, and responsive design.

Next.js React TypeScript Tailwind
Hardware Design
Hardware Design

Single Cycle RISC-V Processor

Complete single-cycle RISC-V processor supporting RV32I instruction set implemented from scratch in SystemVerilog.

SystemVerilog Vivado Assembly

05. Skills & Technologies

Languages

Python
C++
JavaScript
TypeScript
SystemVerilog
SQL

Web Technologies

React
Next.js
Node.js
Tailwind
Supabase

Hardware & Embedded

RISC-V
FPGA
Vivado
Verilator

AI & Data

PyTorch
TensorFlow
HuggingFace
Pandas

06. Get In Touch

I'm currently looking for new opportunities. Whether you have a question, want to collaborate on a project, or just want to say hi, my inbox is always open!

Say Hello